VHDL-2019 Interfaces
Introduction Happy New Year! It’s 2026 and VHDL interfaces, a new feature added in the 2019 language standard, are finally ready for prime-time. VHDL-2019 interfaces solve one of the most painful problems in large VHDL designs: cleanly connecting wide, repetitive interfaces like AXI-Stream, AXI-Lite, or AXI-Full. Until recently, two barriers prevented their use: non-existent synthesis tool support and expensive paid-only simulator support. After spending December developing a set of general-purpose AXI-Stream modules built around interfaces, I can confidently say that both Vivado (synthesis / implementation) and NVC (open-source simulation) now have solid support. VHDL interfaces are ready for new designs in 2026. ...